在本論文中，我們透過預先濺鍍過渡金屬再硫化的方式製備大面積的二硫化鉬薄膜，並且經由控制薄膜成長溫度，可以得到最佳成長溫度為780°C，接著我們控制靶材濺鍍時間，可以達成層數之控制，並經由原子層蝕刻系統，可以準確判斷層數，之後我們將最佳化之薄膜製作成上閘極場效電晶體，並對使用原子層沉積機台成長氧化層進行最佳化之處理，而我們也發現到於成長氧化層之前，於機台中先經過10 cycles的水前處理，能大幅度降低氧化層的表面粗糙度，並且也可以降低界面缺陷使電晶體的遲滯現象達到最小，且載子遷移率大幅度的提升。此外，我們透過預先共鍍過渡金屬再硫化的方式可以成長出合金薄膜，並且可以藉由控制靶材的瓦數來達到不同比例的合金薄膜，而合金薄膜中的二硫化鉬比例越多其薄膜的導電能力也比較好，此結果說明了，二硫化鉬薄膜的導電性比起二硫化鎢薄膜更加優秀，接下來我們於合金薄膜上成長單層的二硫化鉬薄膜形成異質結構薄膜並製作成上閘極場效電晶體，發現單層二硫化鉬薄膜/合金薄膜之異質結構其電流會大幅上升，並且於ID-VGS曲線可以發現有雙極性現象產生，此結果也表明了當單層二硫化鉬與合金薄膜形成異質結構時，會形成2DEG與2DHG之能帶結構，最終，我們成長四層的二硫化鉬薄膜於合金薄膜可以發現雙極性現象之消失，這說明了我們可以藉由控制二硫化鉬薄膜的厚度將異質結構接面隔離，使閘極的控制深度無法到達異質結構介面。

In this thesis, we have demonstrated that large-area molybdenum disulfide (MoS2) can be prepared by sulfurizing the pre-deposited transition metal films. Through tuning the growth temperature, we determine the growth temperature to be 780 °C. In addition, the layer number controllability is also achieved by controlling the sputtering times of the pre-deposited transition metal films. Through atomic layer etching, the layer number can be precise determined. Next, we have demonstrated top-gate MoS2 transistors without the film transferring procedure. With the introduction of H2O pretreatment for the Al2O3 dielectric layer grown on MoS2 surfaces by using ALD, the quality of surface is significantly improved. Moreover, the electrical hysteresis and field-effect mobility of transistor devices are also enhanced. Furthermore, we have demonstrated that alloy thin film can be prepared by sulfurizing the co-sputtering transition metal films. The alloy thin film of different proportions can be determined by controlling the sputtering powers of W and Mo targets. The increasing conductivity of the alloy thin films with increasing Mo compositions suggests that MoS2 is more conductive than WS2 prepared by using this method. Then, we growth monolayer MoS2 on alloy thin film which form 2D hetero-structure, the higher drain currents and ambipolar phenomenon observed for the devices indicate that the close oxide-semiconductor and hetero-structure interfaces will lead to 2DEG and 2DHG structures. Finally, we growth 4-layers MoS2 on alloy thin film and find ambipolar phenomenon disappearing. The results have revealed that we can control the hetero-junction by changing the layer number of MoS2 between gate metal and channel.

摘要 i
Abstract iii
目錄 v
圖目錄 vii
第一章 緒論 1
1-1二硫化鉬與二硫化鎢晶體結構與性質 1
1-2二硫化鉬與二硫化鎢之拉曼光譜分析 2
1-2-1二硫化鉬拉曼光譜分析 3
1-2-2二硫化鎢拉曼光譜分析 3
1-3二硫化鉬與二硫化鎢之光激發螢光光譜分析 4
1-3-1二硫化鉬光激發螢光光譜分析 4
1-3-2二硫化鎢光激發螢光光譜分析 6
1-4二硫化鉬與二硫化鎢之X光光電子能譜分析 7
1-4-1二硫化鉬之X光光電子能譜 7
1-4-2二硫化鎢之X光光電子能譜 8
1-5異質結構之性質 8
1-6過渡金屬硫族化合物之製備方式 9
1-6-1機械剝離法 9
1-6-2化學氣相沉積法 10
1-7研究方向與論文大綱 11
第二章 實驗儀器與實驗方法 13
2-1 薄膜成長系統 13
2-1-1過渡金屬濺鍍沉積系統 13
2-1-2過渡金屬硫化系統 15
2-2材料分析儀器 17
2-2-1拉曼光譜儀 (Raman spectrum) 17
2-2-2光激螢光光譜儀 (Photoluminescence, PL) 19
2-2-3 X光光電子能譜儀 (X - ray Photoelectron Spectroscopy) 19
2-2-4紫外光電子能譜儀 (Ultraviolet Photoelectron Spectroscopy) 20
2-2-5紫外光-可見光光譜儀 (Ultraviolet–visible spectroscopy) 21
2-2-6原子力顯微鏡 (Atomic Force Microscopy) 21
2-2-7穿透式電子顯微鏡 (Transmission Electron Microscopy) 23
2-3電晶體製程設備 23
2-3-1反應式離子蝕刻 (Reactive Ion Etching) 23
2-3-2原子層沉積 (Atomic Layer Deposition) 24
2-3-3熱蒸鍍沉積系統 (Thermal evaporation) 25
2-3-4氧電漿蝕刻 (O2 plasma etching) 26
第三章 二硫化鉬薄膜之最佳化與上閘極場效電晶體 29
3-1二硫化鉬薄膜成長與電晶體之製程 29
3-1-1過渡金屬沉積 29
3-1-2過渡金屬硫化 30
3-1-3上閘極式場效電晶體製程 31
3-2不同成長溫度之二硫化鉬薄膜特性 35
3-2-1以拉曼光譜分析不同成長溫度之二硫化鉬薄膜 35
3-2-2以光激發螢光光譜分析不同成長溫度之二硫化鉬薄膜 36
3-2-3以原子力顯微鏡分析不同成長溫度之二硫化鉬薄膜 37
3-3不同濺鍍秒數之二硫化鉬薄膜特性 38
3-3-1以拉曼光譜分析不同濺鍍秒數之二硫化鉬薄膜 39
3-3-2以原子層蝕刻系統判斷不同濺鍍秒數之二硫化鉬薄膜 39
3-3-3以原子力顯微鏡分析不同濺鍍秒數之二硫化鉬薄膜 40
3-4二硫化鉬之上閘極場效電晶體 41
3-4-1不同次數的水前處理所成長之氧化層之原子力顯微鏡 41
3-4-1不同次數的水前處理之氧化層對電晶體特性的影響 43
3-4-2不同氧化層成長溫度之電晶體特性 44
3-4-4不同次數的水前處理之機制 45
3-5小結 47
第四章 二硫化鉬-二硫化鎢之合金薄膜與異質結構 49
4-1二硫化鉬-二硫化鎢之合金薄膜與異質結構之製備 49
4-1-1二硫化鉬-二硫化鎢之合金薄膜樣品製備 49
4-1-2異質結構薄膜樣品製備 51
4-2二硫化鉬-二硫化鎢之合金薄膜的特性分析 51
4-2-1二硫化鉬-二硫化鎢之合金薄膜的拉曼光譜分析 51
4-2-2二硫化鉬-二硫化鎢之合金薄膜的光激發螢光光譜分析 52
4-2-3二硫化鉬-二硫化鎢之合金薄膜的X光光電子能譜分析 53
4-2-4二硫化鉬-二硫化鎢之合金薄膜的高解析穿透式電子顯微鏡 56
4-2-5二硫化鉬-二硫化鎢之合金薄膜的紫外光光電子能譜分析 58
4-2-6二硫化鉬-二硫化鎢之合金薄膜的紫外光-可見光光譜分析 59
4-3二硫化鉬-二硫化鎢之合金薄膜與異質結構上閘極場效電晶體 61
4-3-1合金薄膜與單層二硫化鉬/合金薄膜異質結構之兩端點元件比較 61
4-3-2單層二硫化鉬/合金薄膜異質結構之薄膜上閘極場效電晶體 63
4-3-3控制異質結構薄膜層數之電晶體影響 65
4-4小結 67
參考文獻 73

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