在本論文中我們模擬矽奈米線穿隧場效電晶體(nanowire tunnel field-effect transistor, NW TFET) 之閘極正交疊/負交疊(gate overlap/underlap) 效應與源極濃度梯度(source doping gradient，SDG) 對TFET元件特性之影響。首先我們在某一源極濃度梯度下模擬不同的閘極正交疊/負交疊元件結構，並觀察其I-V特性。接著我們分別對每種閘極正交疊/負交疊元件結構模擬了5種不同的SDG，並觀察其I-V 特性。模擬結果顯示相較於gate underlap，gate overlap 會有較佳之元件特性，但是元件特性並不會隨著overlap的長度增加而有進一步明顯的改善。另一方面，SDG在overlap元件結構時對元件特性幾乎沒有影響，而在underlap元件結構時則是SDG 越大，元件特性越好。

In this paper ,we simulate Simulation of gate overlap/underlap and source doping gradient of nanowire Tunnel Field-Effect Transistors.
First, we simulate different gate-source overlap/underlap structures in a fixed source concentration gradient and observe their I-V characteristics.
Next, we simulated five different SDGs for each gate-source overlap/underlap structure and observed their device characteristics.
The simulation results show that gate-source overlap structure has better device characteristics than gate-source underlap structure, but the device characteristics do not significantly improve with the increase of the overlap length.
On the other hand, the SDG has Hardly affected on the device characteristics in the gate-source overlap structure, and the larger the SDG in the gate-source underlap structure, the better the device characteristics.

致謝 I
摘要 III
目錄 V
圖目錄 VII
表目錄 XII
第一章 前言 1
1.1前言 1
1.2文獻回顧 3
1-3研究動機 4
第二章 元件結構與模擬方法 5
2.1元件結構 5
2.2 模擬方法 11
2.2.1 模擬流程介紹 11
2.2.2 物理模型 12
第三章 結果與討論 15
3.1電特性之定義 15
3.2 OVERLAP/UNDERLAP效應 16
3.2.1 ID-VG 16
 SDG = 30 nm/dec 16
 SDG = 20 nm/dec 21
 SDG = 10 nm/dec 26
3.2.2 SS 31
3.3 SDG效應 35
3.3.1 ID-VG 35
 gate-source underlap 20 nm 35
 No gate-source overlap/underlap 40
 gate-source overlap 50 nm TFET 45
3.3.2 SS 50
3.4 ION表與I60表 53
第四章 結論 55
4.1結論 55
參考文獻 56
附錄A 元件特性圖 59
附錄B DECKBUILD COMMAND FILE 75

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