在科技快速發展的時代，無線通訊的需求愈來愈大，也更廣為人們所使用，在無線通訊系統中收發機設計為一個重要的關鍵，它依託於電磁波來傳播，其中位於收發機前端的低雜訊放大器需將天線接收到的微弱訊號放大，供後級元件處理，混頻器也扮演著重要的角色，將放大的訊號進行升頻及降頻的轉換，而良好輸入與輸出匹配、高增益、低雜訊、高線性度、低功率消耗與面積小皆是接收機設計的考量，本篇論文研究接收機的設計與製作，以高增益、低雜訊和低功耗為主要設計目標，共提出兩個分別應用於無線個人區域網系統(Zigbee)與車載系統之衛星雷達(FMCW Radar)的電路設計，並且使用Advanced Design System (ADS)電路模擬軟體和台積電0.18μm 1P6M CMOS製程模擬與製作。
第一個為應用於Zigbee之高增益低雜訊的低雜訊放大器，輸入級使用共源極放大器架構，可以提高電壓增益並且抑制雜訊指數，並利用基底偏壓(Body-bias)技術，降低電晶體的操作電壓和臨界電壓，進而降低整體電路功耗，其模擬結果如下，操作頻帶為2.4GHz，增益為20dB，雜訊為2.5dB，IIP3為-21dBm，功率消耗為1.8mW，晶片面積為1.026*0.902 mm^2。
第二個為應用於車載安全系統之高增益低雜訊的天線接收機，整合了低雜訊放大器與混頻器，並改良傳統混頻器架構，RF端使用兩級共源極放大器串接作為輸入級和提高增益值，LO端採用電壓注入法和主動式負載改善線性度，其模擬結果如下，操作頻帶為24GHz，增益為22.2dB，雜訊為8.9dB，IIP3為-13dBm，核心功率消耗為0.96mW，電路總功率消耗為2.7mW，晶片面積為0.942*0.628 mm^2。

In the era of rapid technological development, the demand for wireless communication is growing faster and more used by people. The design of the system transceiver is an important key in the wireless communication. It relies on electromagnetic waves to spread. The low noise amplifier located in the front of the transceiver will amplify the weak signal from the antenna. The Mixer also plays an important role to transform signal . Having good input and output matching, high gain, low noise, high linearity, low power consumption and small area are the considerations of the receiver. This paper studies the design and production of receiver, and the main design goals are high gain, low noise and low power consumption. Two circuit are proposed to apply for Wireless Personal Area Network (ZigBee) and FMCW Radar respectively. Advanced Design System (ADS) is used as the simulation tool. The circuits are manufactured fabricated using tsmc 0.18μm 1P6M CMOS technology and taped out by National Chip Implementation Center (CIC).
The first circuit is a low noise amplifier with high gain and low noise applied for the ZigBee system. The input stage uses a common source amplifier to increase gain and suppress noise. Each body of transistor adds an external bias source, so that the operating voltage and threshold voltage can be reduced effectively. This technique can reduce the overall power consumption. The power gain is 20dB. The noise figure is 2.5dB. The linearity of input-referred third-order intercept point (IIP3) is -21dBm. The total power consumption of this circuit is 1.805mW. The total area of the circuit layout is 1.026*0.902〖 mm〗^2.
The second circuit is a receiver applied for the FMCW Radar system with high gain and low noise. It improves the traditional architecture and integrates the low noise amplifier and the mixer. It's based on the two-stage common-source cascade configuration to provide high gain for the transconductance stage. Using current-bleeding and active load to improve linearity for the switching stage. The power gain is 22.2dB. The noise figure is 8.9dB. The linearity of input-referred third-order intercept point (IIP3) is -13dBm. The core power consumption is 0.96mW. The total power consumption of this circuit is 2.7mW. The total area of the circuit layout is 0.942*0.628〖 mm〗^2.

誌謝 i
中文摘要 ii
Abstract iii
Table of Contents v
List of Figures viii
List of Tables xi
Chapter 1 Introduction 1
1.1. Background and motivation 1
1.2. Introduction of Zigbee band 1
1.3. Introduction of K band 2
1.4. Introduction of FMCW Radar System 2
1.5. Introduction of Vehicle Safety System 2
1.6. Thesis organization 3
Chapter 2 Introduction of Receiver 5
2.1. Introduction the basic parameters of Low Noise Amplifier (LNA) 5
2.1.1. Scattering parameters 6
2.1.2. Noise figure 7
2.1.3. Linearity 8
2.1.4. Stability 10
2.2. Introduction to low noise amplifier Architectures 11
2.2.1. The cascode structure LNA with source degeneration inductance 11
2.2.2. The feedback structure of LNA 13
2.3. Introduction the CMOS Mixer 13
2.3.1. Passive Mixer 15
2.3.2. Active Mixer 15
2.3.3. Parameters of Mixer 21
2.4. In consideration of system level 22
2.5. Literature review 23
2.5.1. A concurrent dual-band 2.4/5.2 GHz low noise Amplifier using gain enhanced techniques [4] 23
2.5.2. A 24GHz down-conversion Mixer with low noise and high gain [6] 24
2.5.3. A wideband CMOS LNA-Mixer for cognitive radio receiver [8] 24
2.6. Design flow 25
Chapter 3 The Proposed LNA 27
3.1. A 0.5V 2.4GHz low voltage low noise amplifiers for ZigBee system application 27
3.2. Input impedance matching 27
3.3. Body bias technology 29
3.4. Consideration of the circuit design 29
3.5. Simulation results 30
3.6. Measured results 37
3.7. Summary and discussion 41
Chapter 4 The Proposed LNA+Mixer 43
4.1. A high gain and low noise figure receiver for FMCW radar application 43
4.2. Design of LNA 44
4.3. Design of Mixer 47
4.3.1. Current bleeding 47
4.3.2. Active load and output buffer 48
4.4. The complete architecture of LNA-MIXER 49
4.5. Simulation results 50
4.6. Measured results 57
4.7. Summary and discussion 60
Chapter 5 Conclusion and Future Work 63
5.1. Conclusion 63
5.2. Future work 63
Reference 65

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