隨著無線通訊系統邁入5G世代，高速傳輸資料是必要的，而在射頻通訊系統中需要穩定、低功耗且低相位雜訊的本地振盪源，因此在壓控振盪器的設計上，低相位雜訊與低功耗為設計最優先考量。本論文使用由台灣積體電路製造公司所提供之(Taiwan Semiconductor Manufacturing, tsmc) 0.18 m 1P6M CMOS製程實現電路模擬與晶片製作。第三章所提出的電路為應用於Sub-6GHz低雜訊電容耦合式正交壓控振盪器，使用分壓方式降低汲極振幅與使用電容進行正交耦合，模擬結果顯示在供應電壓1V下，此振盪器核心功率消耗與可調頻率範圍分別為7.8mW與5 ~ 5.5 GHz；其輸出功率約在-13dBm；相位雜訊在1MHz offset為-113.1 dBc/Hz。
第四章提出的電路為應用Sub-6GHz低功耗低相位雜訊之壓控振盪器，此電路模擬結果顯示在供應電壓1.5V核心功率消耗與可調頻率範圍分別2.9mW與4.7GHz~5.4GHz；輸出功率約在1dBm；相位雜訊在１MHz offset為-117.0 dBc/Hz。

As wireless communication systems entering the 5th generation mobile networks, high-speed data transmission is inevitable. Local oscillation sources are required to be stable, low-power, and low-noise in RF communication systems. Therefore, the design priorities of voltage-controlled oscillators are low phase noise and low power consumption. The tsmc 0.18 μm 1P6M CMOS process technology provided by Taiwan Semiconductor Manufacturing Co. is adopted to realize the proposed circuit and to implement the chip. The proposed capacitor-coupled quadrature VCOs in Chapter 3 was designed to obtain low phase noise. Not only the voltage divided capacitors are used to reduce the drain amplitude but also the capacitor is used for coupling. The core power consumption and tuning range are 7.8mW and 5 to 5.5 GHz, respectively. The output power is about -13dBm. The phase noise is -113.1dBc/Hz@1MHz offset frequency.
In Chapter 4, a low power low phase noise voltage controlled oscillator was presented with a drain resistor for sub-6GHz systems. The simulation results of this circuit show that the core power consumption is 2.9mW at a supply voltage of 1.5V and the operating frequency range is from 4.7GHz to 5.4GHz. The output power is about 1dBm, phase noise is -117.0 dBc / Hz @ 1MHz offset frequency.

第一章 序論 1
1.1 研究背景與動機 1
1.2 Sub-6GHz頻段系統簡介 2
1.3 論文架構介紹 2
第二章 振盪器之基本介紹 5
2.1 壓控振盪器簡介 5
2.1.1 LC壓控振盪器 5
2.2 正交振盪器簡介 6
2.3 相位雜訊介紹 8
2.3.1 相位雜訊定義 9
2.3.2 相位雜訊分析-非時變模型[12] 10
2.3.3 相位雜訊分析-時變模型[3] 11
2.3.4 熱雜訊 14
2.3.5 閃爍雜訊 15
2.3.6 散射雜訊 15
2.4 文獻回顧 16
2.4.1 應用於25GHz鎖相迴路之線性化低相位雜訊壓控振盪器採用自偏壓 16
2.4.2 應用於3.0-3.6 GHz 抑制閃爍雜訊變頻之65nm CMOS 壓控振盪器 18
2.5 設計流程 19
第三章Sub-6GHz電容耦合正交壓控振盪器設計 21
3.1 應用於Sub-6GHz低雜訊電容耦合式正交壓控振盪器設計 21
3.2 電路分析 22
3.3 模擬結果 25
3.4 討論與比較 33
第四章應用Sub-6GHz低功耗低相位雜訊之壓控振盪器結合汲極電阻技術 37
4.1 應用Sub-6GHz低功耗低相位雜訊之壓控振盪器結合汲極電阻技術 37
4.2 電路分析 38
4.3 模擬結果 41
4.4 討論與比較 47
第五章 結論與未來展望 49
5.1 結論 49
5.2 未來展望 49
REFERENCES 51

[1] RF Page “What are 5G frequency bands”
https://www.rfpage.com/what-are-5g-frequency-bands/
[2] B. Razavi, “RF Microelectronics,” Prentice-Hall, 1997
[3] Ali Hajimiri, and Thomas H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE J. Solid-State Circuits, vol. 33, no.2, pp. 179-194, Feb. 1998.
[4] 詹曜宗，“應用於X頻帶使用電容分壓技術之低功耗四相位壓控振盪器設計”，國立東華大學電機工程研究所碩士論文，民國一百零五年。
[5] 詹凱鈞，“應用於C頻段之互補式金氧半導體低相位雜訊C類壓控振盪器暨便壓器耦合四相位壓控振盪器暨利用F類壓控振盪器於C頻段之整數型鎖相迴路暨X頻段III-V族高功率振盪器之研製” ，國立中央大學電機工程學系研究所碩士論文，民國一百零七年。
[6] B. Sadhu, M. A. Ferriss, and A. S. Natarajan, “A linearized, low-phase-noise VCO-Based 25-GHz PLL with autonomic biasing,” IEEE J. Solid-State Circuits, vol. 48, no.5, May 2013.
[7] J. Sun, C. C. Boon, and X. Zhu, “A Low-Power Low-Phase-Noise VCO With Self-Adjusted Active Resistor,” IEEE Microw. Wireless Compon. Lett., vol.26, no. 3, MAR 2016.
[8] P. Shasidharan, H. Ramiah, and J. Rajendran, “A 2.2 to 2.9 GHz complementary class-C VCO with PMOS tail-current source feedback achieving −120 dBc/Hz phase noise at 1 MHz offset,” IEEE Access, vol. 7, pp. 91325–91336, 2019.
[9] S. Levantino, M. Zanuso, C. Samori, and A. Lacaita, "Suppression of Flicker Noise Upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz Band," IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 50-51, 2010.
[10] C.-W. Lim, H.-Y. Noh, and T.-Y. Yun, “Small VCO-gain variation adding a bias-shifted inversion-mode MOS varactor,” IEEE Microw. Wireless Compon. Lett, vol. 27, no. 4, pp. 395–397, Apr. 2017.
[11] S.-J. Kim, D.-I. Seo, J.-S. Kim, “Compact CMOS LiT VCO achieving 198.6 dBc/Hz FoMA,” Electronics Letters, vol. 54, no. 3 pp. 175-177
[12] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, vol. 54, pp. 329-330, Feb. 1966
[13] Y. Wachi, T. Nagasaku, H. Kondoh: “A 28GHz low-phasenoise CMOS VCO using an amplitude-redistribution technique,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, Feb. 2008, pp. 482-630
[14] S.-Y. Lin and H.-K. Chiou, “ A Modified High Phase Accuracy SIC-QVCO Using a Complementary-Injection Technique,” IEEE Microw. Wireless Compon. Lett, vol. 29, no. 3, March 2019.
[15] I-S. Shen, T.-C. Huang, and C. F. Jou , “A Low Phase Noise Quadrature VCO UsingSymmetrical Tail Current-Shaping Technique,” IEEE Microw. Wireless Compon. Lett, vol. 20, no. 7, July 2010.
[16] W. Li and K.-K. M. Cheng, “A Novel, Low-Voltage, Current Reused, Quadrature VCO and Divide-by-4 Frequency Divider Circuit,” IEEE Microw. Wireless Compon. Lett, vol. 23, no. 2, Feb 2013.
[17] Pepe, F., Bonfanti, A., Levantino, S., et al.: “Suppression of flicker noise upconversion in a 65 nm CMOS VCO in the 3.0-to-3.6 GHz band, ” IEEE J. Solid-State Circuits, 2013, 48, (10), pp. 2375–2389
[18] Tong, H., Cheng, S., Lo, Y. c., Karsilayan, A. i., & Silva-Martinez, J. (2012). “An LC quadrature VCO using capacitive source degeneration coupling to eliminate bi-modal oscillation,” IEEE Transactions on Circuits and Systems I: Regular Papers, 59(9),1871-1879.
[19] 許敦智，“0.18μm 互補式金氧半導體高頻壓控振盪器與鎖相迴路設計”，國立交通大學電信工程研究所碩士論文，民國九十五年。
[20] 周健平，“低功率鎖相迴路與電壓控制振盪器之設計與實現”，國立臺灣師範大學電子科技研究所碩士論文，民國一百零二年。
[21] S.-J. Yun, C.-Y. Cha, H.-C. Choi, and S.-G. Lee, “RF CMOS LC-oscillator with source damping resistors,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 9, pp. 511–513, Sep. 2006.
[22] K. Han, H. Shin, and K. Lee, “Analytical drain thermal noise current model valid for deep submicron MOSFETs,” IEEE Trans. Electron Devices, vol. 51, pp. 261–269, 2004.
[23] I-Shing Shen , Christina F. Jou, “A -Band Capacitor-Coupled QVCO Using Sinusoidal Current Bias Techniqu,” IEEE Transactions On Microwave Theory And Techniques, vol. 60, no. 2, Feb 2012.
[24] C. T. Fu and H. Luong, “A 0.8-V CMOS quadrature LC VCO using capacitive coupling,” in IEEE Asian Solid-State Circuits Conference. ASSCC ’07, 2007, pp. 436–439.
[25] M. D. Wei, S. F. Chang, and C. H. Chen, “A low phase-noise QVCO with integrated back-gate coupling and source resistive degeneration techique,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 6, pp. 398–400, Jun. 2009.
[26] B. Razavi, “Design of Analog CMOS Integrated Circuits,” The McGraw-Hill Companies, Inc., 2001
[27] 梁可駿，“以脈衝靈敏函數分析壓控振盪器之相位雜訊特性與K頻段差動低雜訊放大器之研製”，國立中央大學電機工程研究所碩士論文，民國九十六年。