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作者:林沛蓉
作者(英文):Pei-Jung Lin
論文名稱:系統單晶片待機模式電流之偵測與抑制
論文名稱(英文):Detection and Suppression of Standby-Mode Current in SOCs
指導教授:劉耿銘
指導教授(英文):Keng-Ming Liu
口試委員:方士豪
何盈杰
口試委員(英文):Shih-Hau Fang
Ying-Chieh Ho
學位類別:碩士
校院名稱:國立東華大學
系所名稱:電機工程學系
學號:610623002
出版年(民國):107
畢業學年度:107
語文別:中文
論文頁數:51
關鍵詞:靜態漏電流低待機功率環境偵測器自動調整待機功耗
關鍵詞(英文):Static leakage currentlow standby powerenvironmental detectorAutomatic adjustment standby power
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由於IC製造技術發展趨勢將晶圓製程縮小,漏電問題所造成的靜態功率越來越嚴重,在待機模式下都會漏電情況下,減少待機模式下的漏電流為一種能減少功耗的方式,而減少漏電流利用手動偵測並調整不符合效益,因此本論文提出一個環境偵測器,能自動偵測PVT變化調整電壓維持電路,使電路維持在功耗最小的狀態。
本論文提出一個能符合靴帶式電壓維持電路趨勢的環境偵測器,使用TSMC 90 nm CMOS Mixed Signal MS General Purpose Standard Process LowK Cu 1P9M 1.0&3.3V (With UTM)製程設計,操作電壓為0.5V,晶片佈局面積為449.52×350.74f um2,將此環境偵測器應用在有靴帶式電壓維持電路的動態待機控制器上,能自動偵測環境參數並調整為功耗最小的狀態,抑制電源電晶體所產生的漏電流。
Due to the development trend of IC manufacturing technology, the scaling of wafer process is reduced. In addition, the static power caused by the leakage problem is getting more and more serious. Reducing the leakage current in the standby mode is a way to reduce power consumption, and reducing leakage current by manual detection and adjustment is not in line with efficiency. Therefore, this thesis proposed an environmental detector that can automatically detect the PVT change and adjust voltage with maintenance circuit to keep the circuit in the state of minimum power consumption. This proposed environmental detector can meet the trend of the bootstrapped voltage maintenance circuit. It implemented with TSMC 90 nm CMOS Mixed Signal MS General Purpose Standard Process Low K Cu 1P9M 1.0&3.3V (With UTM) process design, operating voltage is 0.5V. The wafer layout area is 449.52 × 350.74f um2. The environment detector is applied to a dynamic standby controller with the bootstrap voltage maintenance circuit. Accordingly, the test chip shows functions of automatic environmental parameter detection and the lowest power adjustment, and then suppress effectively leakage current generated by the transistor.
誌謝 I
摘要 II
Abstract III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 緒論 1
1.1 研究動機 1
1.2 論文大綱 3
第二章 文獻回顧 5
2.1 先進製程的非理想效應 5
2.2 靴帶式升壓電路 7
第三章 電源閘控設計 13
3.1 多臨界電壓CMOS(Complementary Metal Oxide Semiconductor) 13
3.3 自超級截止電源閘控 15
3.4 動態待機控制器 16
3.5 使用電壓維持電路的動態待機控制器 18
第四章 提出自我偵測待機電流電路以及模擬結果 21
4.1 系統單晶片待機模式電流之偵測與抑制 21
4.2電源閘控 22
4.3 應用在電源閘控的靴帶式電壓維持電路 23
4.3.1 控制PMOS開關之升壓電路 23
4.3.2 電荷補償電路 26
4.3.3 靴帶式電壓維持電路 28
4.4 自適應溫度可調環形偵測器 30
4.4.1 延遲單元 30
4.4.2 靴帶式電路 30
4.4.3 自適應溫度可調環境偵測器 31
4.3.4 電路模擬 32
第五章 結論 43
參考文獻 45
[1] Yingchieh Ho , “Leakage Monitoring Technique in Near-threshold Systems with a Time-based Bootstrapped Ring Oscillator,” Asian Test Symposium, 2013 22nd.
[2] K. M. Cao, W. –C. Lee, W. Liu, X. Jin, P. Su, S. K. Fung, J. X. An, B. Yu, C. Hu, “BSIM4 Gate Leakage Model Including Source-Drain Partition,” IEDM Meeting 2000, IEDM Technical Digest, pp. 815-818, December, 2000.
[3] Shin’ichiro Mutoh, et al. , “1-V Power Supply High-speed Digital Circuit Technology with Multithreshold-Voltage CMOS ,” IEEE JSSC, VOL. 30, NO. 8, AUGUST 1995
[4] Alexandre Valentian and Edith Beigné , “Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability ,” IEEE JSSC, VOL. 43, NO. 7, July 2008.
[5] Jian-Shiun Chen, Chingwei Ye, Jinn-Shyan Wang, “Self-Super-Cutoff Power Gating with State Retention on a 0.3V 0.29fJ/Cycle/Gate 32b RISC Core in 0.13μm CMOS,” IEEE ISSCC, pp.426-427, Feb. 2013.
[6] Yingchieh Ho, “A 48.6-to-105.2 μW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications,” IEEE JSSC, VOL. 49, NO. 4, APRIL 2014
[7] Yingchieh Ho and Chen Hsu, “Standby power reduction using dynamic standby control with voltage keeper,” IEICE Electronics Express, Vol.14, No.18, 1–7,September 25, 2017.
[8] Y. Ho and C. Su, “A 0.1–0.3 V 40–123 fJ/bit/ch on-chip data link with ISI-suppressed bootstrapped repeaters,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1242–1251, May 2012.
[9] J. Kil et al., “A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting,” IEEE Trans. Very Large Scale Integr. Syst., vol. 16, no. 4, pp. 456–465, 2008.
[10]J. H. Lou and J. B. Kuo, “A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI,” IEEE J. Solid- State Circuits, vol. 32, pp. 119–121, Jan. 1997.
[11]徐禛,“低功率系統晶片電壓閘控技術”,國立東華大學地基工程學系碩士論文,中華民國105年。
 
 
 
 
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