本論文主要針對「應用於5G系統之低雜訊高增益接收機前端設計」進行研究探討、設計與製作，共提出兩顆皆應用於5G系統的電路設計，並使用台灣半導體研究中心所提供tsmc 0.18um 1P6M CMOS製程模擬及實作，晶片採用on-wafer方式測量。
第一顆為「應用於4.5GHz之低功耗低成本接收機前端設計」，包含了低雜訊放大器和混頻器，此電路第一級採用疊接架構，以一個共源極與共閘級放大器組成，可以提高整體增益及抑制第一級雜訊；且混頻器使用電流注入技術，可有效降低操作電壓，且可以透過調整偏壓來優化整體增益和雜訊。其量測結果如下：操作電壓1.2V，總功率消耗為10.65mW，增益為12.9dB，雜訊指數為15.6dB，輸入三階截斷點為-7.1dBm，輸入返回損耗與輸出返回損耗皆小於-10dB，晶片面積為1.192×1.116mm2。
第二顆為「應用於3.5GHz之低雜訊高增益接收機前端設計」，整合低雜訊放大器和混頻器。低雜訊放大器使用基體偏壓技術來提高轉換增益，另外在不增加功率消耗的同時使用電流再利用架構來提升增益；混頻器負載級採用共模回授架構取代傳統電阻式負載，在不影響線性度的情況下提高轉換增益。傳統式吉伯特混頻器利用差動訊號來解決從LO饋入的電流，加上多閘極電晶體抑制輸入三階諧波項及電流注入來降低開關級的電流並提高增益；緩衝級可以增加轉換增益並達到良好的輸出阻抗匹配。其模擬結果如下：操作電壓1.2V，總功率消耗為7.89mW，轉換增益為26.97dB，雜訊指數為3.77dB，輸入三階截斷點為-31dBm，輸入返回損耗與輸出返回損耗皆小於-10dB，晶片面積為1.019×1.062mm2。

This thesis is focused on the research of “Design of A Receiver Front-end with Low-Phase-Noise and High-Gain for 5G Systems”. Two receivers front-end are proposed for 5G systems application. Both circuits were simulated and fabricated by tsmc 0.18um 1P6M CMOS process technology provided by Taiwan Semiconductor Research Institute. The circuit performances were measured by an on-wafer method.
The first chip is a 4.5GHz receiver front-end with low-power and low-cost for 5G systems application that both low noise amplifier and mixer were integrated together. Amplifiers consisting of common-source and common-gate topologies are used to increase the conversion gain and to inhibit the noise. Using the current bleeding technology can effectively reduce the operating voltage and optimize the overall gain and noise. Under the supply voltage of 1.2V, the following circuit performances are achieved with a gain of 12.9dB. The noise figure is 15.6dB. The IIP3 is -7.1dBm. The total power consumption is 10.65mW. The chip size is 1.192×1.116mm2.
The second chip is a 3.5GHz receiver front-end design with low-phase-noise and high-gain for 5G systems application that both low noise amplifier and mixer were integrated together. Body bias technology is used to increase the conversion gain. Current-reused topology is used to increase gain without increasing the power consumption. The designed mixer is based on a traditional single-balanced Gilbert cell. Differential pairs are adopted in the proposed mixer for solving the leakage current from LO port. Then, the multiple-gate structure is used to suppress the input third order signal and to increase the linearity. The buffer stage increases conversion gain and achieves good output impedance matching. Under the supply voltage of 1.2V, the circuit performances are achieved with a conversion gain of 26.97dB. The noise figure is 3.77dB. The IIP3 is -31dBm. The total power consumption is 7.89mW. The chip size is 1.019×1.062mm2.

第一章 序論 1
1.1 研究背景與動機 1
1.2 5G頻段簡介 1
1.3 5G系統簡介 2
1.3.1 5G特性 3
第二章 無線射頻接收機前端介紹 5
2.1 簡介 5
2.2 低雜訊放大器之基本參數介紹 5
2.2.1 S參數(Scattering Parameters) 6
2.2.2 雜訊指數(Noise Figure，NF) 7
2.2.3 線性度(Linearity) 9
一分貝增益壓縮點(1dB Gain Compression point，P1dB) 9
輸入三階截斷點(Input Third Order Intercept Point，IIP3) 9
2.2.4 穩定度(Stability) 10
2.3 混頻器架構基本介紹 11
2.3.1 被動式混頻器(Passive Mixer) 12
2.3.2 主動式混頻器(Active Mixer) 12
2.4 混頻器之基本參數介紹 16
2.4.1 轉換增益/損耗(Conversion Gain/Loss) 16
2.4.2 雜訊指數 17
2.4.3 隔離度(Isolation) 18
2.5 設計流程概略 18
2.6 文獻回顧 19
2.6.1 應用於3-6.5GHz UWB接收器之順向基體偏壓設計低功耗放大器 19
2.6.2 應用於3.1-4.8 GHz UWB MB-OFDM接收器使用電流注入技術之CMOS混頻器設計 20
第三章 應用於4.5GHz之低功耗低成本 接收機前端設計 21
3.1 低雜訊放大器電路設計 23
3.1.1 輸入匹配電路 23
3.1.2 電壓增益 24
3.1.3 雜訊 26
3.2混頻器電路設計 26
3.2.1 LO輸入匹配電路 27
3.2.2 電流注入技術(Current Bleeding Technology) 28
3.2.3 主動式負載之負回授電路 29
3.3 模擬及量測結果 31
3.3.1 模擬結果 32
3.3.2 量測結果 39
3.4 討論及比較 44
第四章 應用於3.5GHz之低雜訊高增益 接收機前端設計 50
4.1 低雜訊放大器電路設計 52
4.1.1 輸入匹配電路 53
4.1.2 電壓增益 54
4.1.3 電流再利用設計(Current-reused) 55
4.1.4 基體偏壓技術(Body bias technology) 56
4.2 混頻器電路設計 57
4.2.1 LO輸入匹配電路 58
4.2.2 主動式負載之負回授電路 59
4.3 模擬及量測結果 60
4.3.1 模擬結果 61
4.3.2 量測結果 68
4.4 討論及比較 71
第五章 結論與未來方向 81
5.1 結論 81
5.2 未來方向 81
參考文獻 83

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