本論文主要對於「5G系統接收機前端寬頻整合設計」進行設計研究與製作，共提供兩顆應用於5G系統中Sub-6G頻寬的電路設計，電路使用台灣半導體研究中心所提供TSMC 0.18μm 1P6M CMOS 製程進行模擬及實作，晶片採用on-wafer方式測量。

第一顆為「應用於Sub-6G系統高增益低雜訊放大器採用電流再利用技術」，此電路採用共閘極形成寬頻輸入匹配，並透過電流再利用技術形成疊接架構，再利用偏壓電流源控制第一級的電流可調範圍；後接疊接放大器(Cascode Amplifier)架構，提高寬頻電路中頻增益，得到整體電路的增益平坦度；最後為共汲級放大器(Common Drain Amplifier；CD Amp)架構，作為緩衝放大器，主要為獲得良好的寬頻輸出阻抗匹配。量測電路效能如下:操作頻寬為2.0~6.0 GHz，輸入返回損耗與輸出返回損耗皆小於-10 dB，電路增益為18.68±2.34 dB，雜訊指數為 6.25±0.76 dB，在操作電壓1.4V下，電路總功率消耗為 10.5mW，輸入三階截斷點在3.6 GHz時為 dBm，一分貝增益壓縮點在3.6 GHz時為dBm，晶片總面積為 1.262×1.438 mm2。

第二顆為「應用於Sub-6G系統接收機前端寬頻電路設計」，電路整合低雜訊放大器和混頻器，低雜訊放大器採用帶通濾波器與回授電路提升輸入匹配，並透過疊接架構提升隔離度；混頻器使用共模回授架構可以提高轉換增益且避免過多壓降，而不去降低線性度，並以RC串聯提升LO端的輸入匹配，還有使用電流注入將降低開關級的電流，加入Buffer在最後做為緩衝級提升增益並匹配。量測電路效能如下:操作頻寬為0.7~6.0 GHz，輸入返回損耗與輸出返回損耗皆小於-10 dB，LO端輸入返回損耗盡可能以寬頻方式達成小於-10 dB，電路轉換增益為20.502±2.8 dB，雜訊指數為11.42 dB，隔離度皆小於-10dB，在操作電壓1.3 V下，電路總功率消耗28.73mW，輸入三階截斷點在3.5 GHz時為9dBm，一分貝增益壓縮點在3.5GHz時為dBm，晶片總面積為1.275×1.138 mm2。

This thesis is focused on the design research and production of "Design of a wideband receiver frond-end circuit for 5G systems ". A total of two circuit designs for Sub-6G bandwidth in 5G systems are provided. Both of the circuits were simulated and fabricated by TSMC 0.18μm 1P6M CMOS process provided by Taiwan Semiconductor Research Institute. The chip was measured by an on-wafer method.
The first chip is " A high gain low noise amplifier with current-reuse technology for Sub-6G systems ". This circuit used to input wideband matching by a common gate, and to consisting cascade structure by current reused technology ,and to controlling current adjustable range of the first stage by bias current source. Followed by the Cascode Amplifier architecture to increase the intermediate frequency gain of the wideband circuit, and to obtain the gain flatness of the overall circuit; finally, the Common Drain Amplifier (CD Amp.) architecture, as a buffer amplifier, was mainly for obtaining good broadband output impedance matching. The following circuit performances are operated bandwidth is 2.0~6.0 GHz, the input return loss and output return loss were both less than -10 dB, the circuit gain is18.68±2.34 dB, the noise figure is 6.25±0.76 dB, and the total power consumption under the supply voltage of 1.4 V is 10.5mW, the IIP3 is -15.2 dBm, the P1dB is -24 dBm, and the total chip area is 1.262×1.438 mm2.
The second chip is "Design of a wideband receiver frond-end circuit for Sub-6G systems ".Low noise amplifier and mixer were integrated. The low noise amplifier used to improve input matching by band pass filter and feedback circuit, and to improved isolation by cascode. The mixer used to increase the conversion gain and avoid excessive voltage drop without reducing linearity with common-mode feedback, and to improve the input matching at the LO terminal with RC series, and to reduce current of switching stage by current injection. The buffer added to as a buffer stage at the end to increase the gain and matching. The following circuit performances are operated bandwidth is 0.7~6.0 GHz, the input return loss and output return loss are both less than -10 dB, the conversion gain is 20.502±2.8 dB, the noise figure is 11.42 dB, the isolation is less than –10 dB. The total power consumption under the supply voltage of 1.3 V is 28.73mW,, the IIP3 is -9 dBm, the P1dB is -20.8 dBm, and the total chip area is 1.275×1.138 mm2.

誌謝 I
中文摘要 III
ABSTRACT IV
目錄 V
圖目錄 VIII
表目錄 XIV
第一章 序論 1
1.1 研究背景與動機 1
1.2 Sub-6GHz頻段系統簡介 3
1.3 無線射頻收發機架構介紹 3
1.4 論文架構介紹 4
第二章 射頻接收機子電路基本介紹 5
2.1 簡介 5
2.2 低雜訊放大器及基本參數介紹 5
2.2.1 散射參數(Scattering Parameters, S-Parameters) 5
2.2.2 雜訊指數(Noise Figure, NF) 7
2.2.3 線性度(Linearity) 12
2.2.4 穩定度(Stability) 14
2.3 混頻器及基本參數介紹 15
2.3.1 被動式混頻器(Passive Mixer) 16
2.3.2 主動式混頻器(Active Mixer) 16
2.4 混頻器重要參數介紹 20
2.4.1 轉換增益/損耗(Conversion Gain/Loss) 21
2.4.2 雜訊指數(Noise Figure) 21
2.4.3 隔離度(Isolation) 23
2.4.4 靈敏度(Sensitivity) 23
2.4.5 動態範圍(Dynamic Range) 24
2.5 設計流程 24
2.6 文獻回顧 26
2.6.1 應用於3~10.5GHz低低功耗低雜訊放大器採用電流再利用和基體偏壓設計技術(Low voltage and low power UWB CMOS LNA using current-reused and forward body biasing techniques) 26
2.6.2 自適應波束賦形超寬頻脈衝RF前端接收器之低雜訊放大器 28
2.6.3 應用於3.1-4.8GHz MB-OFDM接收器採用電流注入技術 29
第三章 Sub-6G系統低雜訊放大器設計 31
3.1 應用於Sub-6G系統高增益低雜訊放大器採用電流再利用技術 31
3.2 電路分析 33
3.2.1 電流再利用技術(Current-reused) 33
3.2.2 雙諧振網路架構(Dual-resonance Loading Network) 34
3.2.3 輸入阻抗匹配(Input impedance matching) 35
3.2.4 電路增益(Power Gain) 36
3.2.5 雜訊(Noise) 40
3.3 模擬結果 41
3.4 量測結果 53
3.5 結論與比較 57
第四章 Sub-6G系統接收機前端設計 63
4.1 應用於Sub-6G系統接收機前端寬頻電路設計 63
4.2 低雜訊放大器電路分析 65
4.2.1 輸入匹配阻抗(Input impedance matching) 66
4.2.2 電路增益(Power Gain) 67
4.2.3 雜訊(Noise) 68
4.3 混頻器電路分析 69
4.3.1 電流注入技術(Current Bleeding) 70
4.3.2 主動式負載電路 72
4.3.3 LO端輸入阻抗匹配(LO Input impedance matching) 73
4.3.4 電路增益(Power Gain) 74
4.4 模擬結果 75
4.5 量測結果 91
4.6 結論與比較 97
第五章 結論與未來展望 103
5.1 結論 103
5.2 未來展望 103
參考文獻 105

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