碳化矽作為半導體材料在各方面都優於矽材料，因為有著比矽高10倍的崩潰電場、高開關速度和高導熱率，所以在高壓高頻高溫的環境下將有機會取代矽材料半導體，這是眾所皆知的。因此本篇論文主要是在探討使用6H-SiC材料下，比較UMOS和DMOS改變漂移區摻雜濃度、漂移區厚度對導通電阻、崩潰電壓、品質因數的影響。模擬結果得知，當增加漂移區摻雜濃度和減少漂移區厚度時，可以降低導通電阻，反之當降低漂移區摻雜濃度和增加漂移區厚度時，可以提高崩潰電壓。另外DMOS元件中的JFET區域長度會影響導通電阻，但是對BV影響並不大。模擬得出元件的最佳值，當UMOS在漂移區摻雜濃度為1*1016 cm-3、漂移區厚度為8.5 m下，有著8.0 mΩ-cm2的Ron,sp、1091 V的BV以及149 MW/cm2的FoM，而當DMOS元件漂移區摻雜濃度為5*1015 cm-3、漂移區厚度為10.5 m下，有著1790 V的BV，Ron,sp為26.4 mΩ-cm2以及FoM為121 MW/cm2。

As a semiconductor material, silicon carbide is superior to silicon material in all aspects, because it has 10 times the breakdown field higher than silicon, high switching speed and high thermal conductivity than, so it will have the opportunity to replace silicon material semiconductor in the environment of high voltage, high frequency and high temperature, which is widely known. Therefore, this paper mainly discusses the effect of changing the drift region doping concentration and the drift region thickness between 6H-SiC UMOSFET and 6H-SiC DMOSFET on the specific on-resistance, breakdown voltage and figure of merit. The simulation results show that when the drift region doping concentration is increased and the drift region thickness is decreased, the specific on-resistance can be reduced, and conversely when the drift region doping concentration is decreased and the drift region thickness is increased, the breakdown voltage can be increased. In addition, the DMOSFET device will affects the specific on-resistance in the JFET region length, but it has little effect on the breakdown voltage. The device of the best value is obtained by simulation. When the drift region doping concentration is 1*1016 cm-3 and the drift region thickness is 8.5 m of the UMOSFET, the breakdown voltage of 1091 V, specific on-resistance of 8.0 mΩ-cm2 and FoM of 149 MW/cm2, when the drift region doping concentration is 5*1015 cm-3 and the drift region thickness is 10.5 m of the DMOSFET, the breakdown voltage of 1790 V, specific on-resistance of 26.4 mΩ-cm2 and FoM of 121 MW /cm2.

致謝 i
摘要 ii
Abstract iii
目錄 v
圖目錄 vii
表目錄 xii
第一章 緒論 1
第一節 前言 1
第二節 文獻回顧 2
第三節 研究動機 4
第二章 元件結構與模擬方法 5
第一節 元件結構 5
第一條 UMOS元件 5
第二條 DMOS元件 8
第二節 模擬方法 11
第一條 模擬流程介紹 11
第二條 物理模型 11
第三條 Ron,sp、BV、FoM之定義 12
第三節 DMOS元件中JFET長度最佳化 14
第三章 模擬結果與討論 18
第一節 UMOS漂移區摻雜濃度及漂移區厚度效應 18
第一條 UMOS漂移區摻雜濃度效應 19
第二條 UMOS漂移區厚度效應 25
第二節 DMOS漂移區摻雜濃度及漂移區厚度效應 31
第一條 DMOS漂移區摻雜濃度效應 32
第二條 DMOS漂移區厚度效應 38
第三節 總結 44
第一條 UMOS和DMOS漂移區摻雜濃度效應 44
第二條 UMOS和DMOS漂移區厚度效應 47
第四章 結論 50
參考文獻 51
附錄 54
附錄A 6H-SiC UMOS input file 54
附錄B 6H-SiC DMOS input file 63
附錄C 各種UMOS和DMOS的ID-VG及ID-VD圖 72

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