實體記憶體保護機制(Physical Memory Protection，PMP)對於一般程式設計者來說是個比較陌生的機制，在x86這些平台都是使用記憶體管理單元 (Memory Management Unit，MMU)，專門處理虛擬記憶體與實體記憶體之間的轉址，同時做記憶體位址的保護，會使用MMU的處理器架構通常是有較大的定址空間的需求，能處理較多的運算，同時 電路也較複雜。
實體記憶體保護機制相較簡單於記憶體管理單元的電路設計，所需要的邏輯運算單元因此較少，適合用於當代流行的物聯網 (Internet of Things ，IoT) 嵌入式系統的處理器架構，由於嵌入式系統相較於一般個人電腦處理的運算較少，因此不需要太大的定址空間，也可以節省成本，同時達到低功耗的效果。
本論文根據RISC-V開源指令集的特權規格書之實體記憶體保護暫存器規格以硬體描述語言 (Verilog) 實作此機制，透過硬體描述語言模擬程式 (Verilator) 將硬體描述語言轉換成個人電腦可以執行的程式碼 (C++、SystemC) 模擬電路運作，接著撰寫組合語言並編譯成執行檔輸入該模擬程式驗證設計的電路功能是否正確。
最後，希望透過此論文為RISC-V開源生態系盡一份心力，也讓更多人能了解RISC-V指令集架構。

In opinion of normal programmer, Physical Memory Protection is kind of strange mechanism. The personal computers we used to program every day are all based on X86 architecture Central Processing Unit (CPU), and the architecture usually support Memory Manage Unit (MMU), which has the function of memory protection. The main purpose of MMU is dealing with the address transfer between Virtual address and Physical address. However, what kind of CPU should have MMU is depend on the requirement of address space.
The implementation of Physical Memory Protection (PMP) is simple than MMU, and the requirement of logic unit in PMP is also less than in MMU, so PMP is more adapted to the modern Internet of Things (IoT) device, which need less memory resources and transistors. As a result, PMP can reach the goal of saving cost and energy.
This research is based on RISC-V architecture official privileged specification to implement PMP；First, we implemented PMP unit by Hardware Description Language “Verilog”, and simulated the code by the simulation software “Verilator”, which can transfer Verilog to C++, then, wrote assembly code to verify the PMP unit.
Finally, I hope to do my effort in the eco-system of RISC-V and let more people learn how RISC-V works.

第一章 緒論 1
1-1 綜述 1
1-2 動機與目的 2
1-3 論文架構 3
第二章 文獻探討 5
2-1 Aquila架構介紹 5
2-2 支援實體記憶體保護的開源處理器介紹 8
2-2-1 Ibex 8
2-2-2 Chromite 9
2-3 不同硬體架構之PMP實作 11
2-4 RISC-V介紹 12
2-4-1 RISC-V指令集介紹 12
2-4-2 特權模式 16
2-4-3 控制與狀態暫存器 16
2-4-4 RISC-V Interrupt and Exception介紹 18
2-4-5 RISC-V架構與作業系統協作 21
第三章 Physical Memory Protection 介紹 22
3-1 Logical/Physical address space 22
3-2 Physical Memory Protection介紹 23
3-2-1 pmpcfg與pmpaddr介紹 23
3-2-2 pmpcfg規格介紹 25
第四章 Physical Memory Protection設計與實作 28
4-1 PMP於Aquila core架構之實作 28
4-2 PMP Unit實作 30
第五章 實驗結果 33
5-1 實驗環境 33
5-2 實驗流程 33
5-3 實驗結果 34
第六章 結論與未來展望 38
參考文獻 40

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