本論文的研究目的是將原本為一個軟體機制的context switch，更改為一個RISC-V指令集架構下的CPU硬體指令和硬體模組，來減少讀寫記憶體次數以及指令執行多寡來增進執行時的效率。上下文轉換為切換工作時必須要執行的動作，對於CPU處理工作是額外負擔，因此透過實作加速器來增進效率。另外，也新增軟體的exception handler來處理context switch指令的例外情況。

實作完成的RISC-V核心，在Verilator模擬的環境下通過RISC-V官方測試程式的驗證，以及作業系統測試加速器的效能和正確性，根據實驗結果，若是在hit rate=60%的情況下，且其餘miss情況平均發生，比起原本的context switch時間會快約2.68倍，效率提升約62%。

The purpuse of this research is to transform the original software-based context switch mechanism into a hardware instrution and moudule based on the RISC-V instruction set architecture.The aim is to reduce the number of memory accesses and the amount of executed instructions in order to enhance the efficiency during execution.
The actions performed during context switching, which are necessary for task switching, impose an additional burden on the CPU for task execution. Therefore, an accelerator is implemented to improve efficiency. Additionally, a new exception handler is added to the software to handle exceptional cases during context switch instruction.

The implemented RISC-V core has been verified through the validation of RISC-V official test programs in a Verilator simulation environment. The performance and correctness of the accelerator have also been tested using the operating system. In our experimental results, when the hit rate is 60%, the new context switch speed is approximately 2.68 times faster than the original context switch. The speedup of the modification is approximately 62%.

一、緒論 1
1.1 研究目的和動機 1
1.2 RISC-V 1
1.2.1 RISC-V 指令集架構 2
1.2.2 特權模式 3
1.3 RISC-V 開源處理器 4
1.3.1 Ibex 4
1.3.2 XuanTie C910 5
1.3.3 Aquila SOC 6
1.4 FreeRTOS 8
1.4.1 Task 8
1.4.2 Schdule 9
1.4.3 FreeRTOS 應用 10
1.5 RISC-V Soc 11
二、研究方法13
2.1 CTX 硬體設計原理 13
2.1.1 Context Switch 13
2.1.2 FreeRTOS 的Context Switch 14
2.2 改良context switch 17
2.3 中斷和異常 19
2.3.1 中斷原理 19
2.3.2 處理流程 20
三、CTX 模組實作 23
3.1 CTX 架構 23
3.2 CTX 新增CSR 暫存器 24
3.3 CTX 模組 25
3.3.1 CTX 模組介紹 25
3.3.2 CSR 模組修改 29
3.3.3 Pipeline Control 30
3.4 CTX 新增指令 31
3.5 更改RISC-V Compiler 33
3.5.1 RISC-V opcode tools 33
3.5.2 更改binutils 34
3.6 CTX Exception 37
四、實驗結果 39
4.1 實驗環境 39
4.2 實驗方法 39
4.3 實驗結果 40
4.3.1 RISC-V 官方指令測試程式 40
4.3.2 OS 功能驗證 41
4.3.3 時序圖時序驗證 44
4.3.4 效能測試 45
五、總結 49
5.1 結論 49
5.2 未來與展望 49
參考文獻 51

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