科技不斷的進步，物聯網的市場規模越來越大，半導體產業也不斷地追求更小的晶片面積，因此擁有更低功耗、功能及效能的精簡指令集電腦（Reduced Instruction Set Computer，RISC）便不斷誕生。RISC-V有著精簡模組化、開源免費的特性，也沒有複雜的指令解碼邏輯，使得基於RISC指令集設計的處理器，擁有較低的開發成本、較高的客製化彈性，而且能花費較少的時間，來載入和存儲值到內存記憶體。這使得RISC體系結構的處理器在智慧手機、平板電腦、遊戲機台等設備上被廣泛應用。

本論文的研究採用RISC-V模組來建構我們所設計的處理器，並據以實現RV32I指令集。處理器架構分成五大部分，包括讀取指令、指令解碼、執行指令、資料存取、寫回資料。為了使處理器更有效率並改善生產率（Throughput），採管線化（Pipeline）設計，使擁有解決衝突（Hazard）。並增添分治法（Divide and Conquer）的乘積累加運算（Multiply Accumulate，MAC）硬體單元，提高應用運算效率和實用性。卷積運算（Operations of Convolution）、矩陣運算（Operations of Matrix）等，均可細分為數個乘積累加運算指令，提高上述應用的運算速度。

本論文的實作及模擬部分，使用Verilog寫成RTL（Register-Transfer Level）設計模擬，並採用Verdi Automated Debug System來驗證電路架構的正確性。我們採用TSMC 90奈米製程，經由Design Compiler進行電路合成與電路最佳化，最後使用Innovus進行電路布局，經過多道設定及驗證完成。我們的設計與實作驗證了RISC-V 加入 MAC 硬體單元的可行性，並可據以提升許多應用的執行速度。

As technology continues to advance and the market for the IOT grows, the semiconductor industry continues to pursue lower power consumption, more features, and better performance in a smaller chip. As a result, Reduced Instruction Set Computer （RISC） was born, which is modular, open source, and free of complex instruction decoding logic. It makes RISC based processors less costly to develop, more flexible to customize, and less time to load and store values into internal memory. Hence, RISC architecture processors are increasingly used in smartphones, tablets, gaming consoles, and other smart devices.

This thesis presents the design and implementation of a RISC-V processor, which is based on the RV32I instruction set. The design can be divided into five major parts: Instruction Fetch, Instruction Decode, Execution or Address Calculation, Data Memory Access, and Write Back. In order to make the processor achieve higher throughput, a pipeline architecture is employed and can resolve pipeline hazards. To make the processor more efficient and versatile, we add a Multiply Accumulate（MAC）hardware unit in the datapath. Operations of convolution, matrix multiplication, and many others can be decomposed into several multiply accumulate instructions. With this new hardware unit, many applications with such operations can be improved.

We employed cell-based design flow for our implementation. We designed this processor in Verilog, and the Verdi Automated Debug System is used to verify the correctness of the circuit architecture. Design Compiler is used for circuit synthesis and circuit optimization. Finally, the circuit layout was done by Innovus, and after multiple setups and verifications, it was completed. It showed that incorporating a MAC unit in a RISC-V processor is feasible and practical, and can enhance the performance of many applications.

第一章　緒論 1
1.1 研究動機與目的 1
1.2 研究貢獻 2
1.3 論文架構 2
第二章 RISC-V指令集架構 3
2.1 RISC與CISC之比較 3
2.2 RISC-V的開放設計 4
2.3 不同的指令架構 4
第三章 設計架構與實作 6
3.1 RISC-V Register Convention 6
3.2 架構 15
3.2.1 取得指令 16
3.2.2 指令解碼和讀取暫存器 17
3.2.3 執行或位址運算 18
3.2.4 記憶體讀取 20
3.2.5 寫回暫存器 21
3.2.6 乘法器 22
3.3 衝突 23
3.3.1 結構衝突 23
3.3.2 資料衝突 24
3.3.3 控制衝突 27
第四章 實作與結果 30
4.1 實驗環境 30
4.2 效能量測與比較 31
4.2.1 乘法器和算術邏輯單元 31
4.2.2 結構衝突 32
4.2.3 資料衝突 32
4.2.4 控制衝突 33
4.2.5 乘積累加運算MAC差異 33
4.2.6 RISC-V CPU 33
4.3 電路合成與數據 35
第五章 結論與未來展望 38
參考文獻 39

[1] A. Waterman, Y. Lee, D. Patterson and K. Asanovic, “The RISC-V instruction set manual. Volume I: User-Level ISA Document Version 1.1”, 2014.
[2] “What Is RISC?” https://www.arm.com/zh-TW/glossary/risc.
[3] V. V. Zunin and I. I. Romanova, “Parameterized Computing Module Generator Based on a Systolic Array,” IEEE International Conference on Industry 4.0, Artificial Intelligence, and Communications Technology, pp. 217-220, 2022.
[4] M. Kalmath, A. Kulkarni, S. V. Siddamal and J. Mallidu, “Implementation of 32-bit ISA Five-Stage Pipeline RISC-V Processor Core.” In Artificial Intelligence and Sustainable Computing, pp. 243-251, Springer, 2022.
[5] Y. Ju and J. Gu, “A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance,” In IEEE Journal of Solid-State Circuits, vol. 58, no. 1, pp. 216-226, 2023.
[6] X. Si et al., “15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips,” IEEE International Solid- State Circuits Conference - （ISSCC）, pp. 246-248, 2020.
[7] S. K. Moore, “Esperanto Techology’s Chip Heralds New Era In Open-Source Architecture,” https://spectrum.ieee.org/risc-v-ai, IEEE Spectrum, 2022.
[8] D. L. T. Wong, Y. Li, D. John, W. K. Ho and C. H. Heng, “Low Complexity Binarized 2D-CNN Classifier for Wearable Edge AI Devices,” IEEE Transactions on Biomedical Circuits and Systems, 16（5）, 822-831, 2022.
[9] M. Shaaban, “Complex Instruction Set Computer （CISC）,” http://http://meseec.ce.rit.edu/eecc250-winter99/250-2-14-2000.pdf.
[10] M. Gautschi, P. D. Schiavone, A. Traber, I. Loi, A. Pullini, D. Rossi, and L. Benini, “Near-Threshold RISC-V Core with DSP Extensions for Scalable Iot Endpoint Devices,” IEEE Transactions on Very Large Scale Integration （VLSI） Systems, 2017.
[11] D. Banatao, “Driving the Future of Chip Innovation: Top Three Reasons to Adopt RISC-V,” https://www.computer.org/publications/tech-news/trends/reasons-to-adopt-risc-v, IEEE Computer Society, 2022.
[12] D. A. Patterson and J. L. Hennessy, Computer Organization and Design RISC-V, Morgan Kaufmann, 2017.
[13] J. Mallidu and S. V. Siddamal, “A Survey on In-Order 5-Stage Pipeline RISC-V Processor Implementation,” Information and Communication Technology for Competitive Strategies, pp. 777-784, Springer, 2023.
[14] R. Jain and N. Pandey, “Approximate Karatsuba Multiplier for Error-Resilient Applications,” AEU-International Journal of Electronics and Communications, 2021.
[15] A. Raveendran, V. B. Patil, D. Selvakumar and V .Desalphine, “A Risc-V Instruction Set Processor-Micro-Architecture Design And Analysis,” IEEE International Conference on VLSI Systems, Architectures, Technology and Applications, pp. 1-7, 2016.
[16] A. Waterman, Y. Lee, D. Patterson and K. Asanovic, The RISC-V Instruction Set Manual. Volume I: User-Level ISA Document Version 2.2, 2017.
[17] E. Lyons, V. Ganti, R. Goldman, V. Melikyan and H. Mahmoodi, “Full-Custom Design Project for Digital VLSI And IC Design Courses Using Synopsys Generic 90nm CMOS Library,” IEEE International Conference on Microelectronic Systems Education, pp. 45-48, 2009.
[18] K. P. Ghosh and A. K. Ghosh, “Technology mediated tutorial on RISC-V CPU core implementation and sign-off using revolutionary EDA management system （EMS） — VSDFLOW,” China Semiconductor Technology International Conference （CSTIC）, pp. 1-3, 2018.
[19] V. Viswanathan, J. Runhaar, D. Reed and J. Zhao, “Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM and Verdi Transaction Debugging,” International Workshop on Microprocessor and SOC Test and Verification （MTV）, pp. 25-29, 2016.
[20] “Design Compiler,” https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/dc-ultra.html.